1. Field of the Invention
The present invention relates to pipelined ADCs, and more particularly to a 1-bit cell circuit used in pipelined ADCs.
2. Description of the Related Art
In mixed modes circuits, ADC (Analog-Digital-Converter) is an inevitable part. Recently, pipelined ADC is widely adopted due to its concise structure and superior performance. Please refer to FIG. 1, which shows the typical architecture of a prior art 1-bit cell of a pipelined ADC. The 1-bit cell has a sampling phase and a charge transfer phase during a clock cycle. As shown in FIG. 1, the 1-bit cell includes an OTA (Operational Transconductance Amplifier) 101, four matched capacitors 102˜105, a first set of switches 106˜113, a second set of switches 114˜121, two multiplexers 122 and 123, and two latched comparators 124 and 125.
The OTA 101 is used to generate a residue output Vout according to an input signal Vin, wherein the residue output Vout is composed of a positive output Voutp and a negative output Voutn, and the input signal Vin is composed of a positive input signal Vinp and a negative input signal Vinn. The matched capacitors 102˜105 are used to hold a sampled voltage of the input signal Vin. The first set of switches 106˜113 are closed for sampling the input signal Vin during the sampling phase. The second of switches 114˜121 are closed during the charge transfer phase to make the matched capacitors 102˜105 and the OTA 101 form a negative feedback circuit to generate the residue output Vout. The two multiplexers 122 and 123 are used to respectively provide a first multiplexer output voltage and a second multiplexer output voltage which are selected from a group consisting of a negative reference voltage Vrefn, a positive reference voltage Vrefp and a ground voltage according to two select signals bp and bn, wherein bp is a positive bit signal and bn is a negative bit signal. When bp=0 and bn=0, the first multiplexer output voltage and the second multiplexer output voltage are both connected to the ground voltage; when bp=0 and bn=1, the first multiplexer output voltage is connected to the negative reference voltage Vrefn and the second multiplexer output voltage is connected to the positive reference voltage Vrefp; and when bp=1 and bn=0, the first multiplexer output voltage is connected to the positive reference voltage Vrefp and the second multiplexer output voltage is connected to the negative reference voltage Vrefn. The comparator 124 is used to generate the positive bit signal bp according to voltage comparison of the input signal Vin and a first reference voltage Vref/4, and the comparator 125 is used to generate the negative bit signal bn according to voltage comparison of the input signal Vin and a second reference voltage −Vref/4, wherein the Vref is equal to the voltage difference between the Vrefp and the Vrefn. When Vin is between −Vref/4 and Vref/4, (bp, bn) is (0,0); when Vin is smaller than −Vref/4, (bp, bn) is (0,1); and when Vin is greater than Vref/4, (bp, bn) is (1,0).
During the sampling phase, the input signal Vin is sampled and hold, and the positive bit signal bp and the negative bit signal bn are generated. Please refer to FIG. 2a, which shows an illustrating diagram of the sampling phase of the prior art 1-bit cell. As shown in FIG. 2a, the top plates of the capacitor 102 and the capacitor 103 are connected to the positive terminal of the Vin, and the top plates of the capacitor 104 and the capacitor 105 are connected to the negative terminal of the Vin, and all the bottom plates of the capacitors 102, 103, 104 and 105 are connected to the ground. The comparator 124 and 125 respectively generates the positive bit signal bp and the negative bit signal bn for the charge transfer phase.
During the charge transfer phase, the residue output is generated. Please refer to FIG. 2b, which shows an illustrating diagram of the charge transfer phase of the prior art 1-bit cell. As shown in FIG. 2b, due to the virtual ground of the OTA 101 in negative feedback, there will be charge drawn from the Vref, flowing through the capacitors 102˜105 to generate the residue output Vout=2×Vin−(bp−bn)×Vref.
However, as the Vin is a varying signal, the charge delivered by the Vref will be different. That is, the loading of the Vref will be varying and dependent on the input signal Vin. The total amount of charge Q taken from the Vref by each 1-bit cell can be easily computed as being the capacitance of the capacitor 102, the capacitor 104 times the voltage difference between the final voltage appearing on the capacitor 102, the capacitor 104 at the end of the charge transfer phase, and the voltage appearing on the capacitor 102, the capacitor 104 at the beginning of the charge transfer phase. For a first order analysis, assuming complete settling at each clock phase, and neglecting any mismatch between the positive and negative channels of the differential architecture, e.g. consider the capacitance of the capacitor 102=Csp, the capacitance of the capacitor 104=Csn, and Csp=Csn=Cs. The total amount of charge Q is derived according to bit decision as follows:for b=+1(bp=1&bn=0), Q=Csp*(Vrefp−Vinp)=−Csn*(Vrefn−Vinn)=Cs*(Vref−Vin)/2;for b=−1(bp=0&bn=1), Q=Csn*(Vrefp−Vinn)=Csp(Vrefn−Vinp)=Cs*(Vref+Vin)/2; andfor b=0(bp=0&bn+0), Q=0.
The minimal input voltage Vin yielding a positive bit decision (b=+1) is Vref/4, and the maximal amount of charge thereof arises to: Q,max=Cs*(Vref−Vref/4)/2=3*Cs*Vref/8=0.375*Vref. The negative (b=−1) bit decision yields the same maximal value for Q (the input signal Vin gets the opposite value, and the connection of the capacitor 102, the capacitor 104 to the reference voltage Vref are cross-swapped). Since there is no load at all applied on the reference voltage Vref for a null bit decision (b=0), the total variation (with the input signal Vin) of the charge taken from the reference voltage Vref is thus: Q,var=Q,MAX−0=0.375*Cs*Vref.
Since the loading of the reference voltage Vref depends on the input signal Vin, complete settling of voltage on the sampling capacitor is then needed to prevent sampling noise. However, this implies a longer sampling time. If high speed is required, then more power has to be burned on the reference voltage buffer to shorten the settling time.
Therefore, there is a need to provide a solution capable of reducing the power consumption and eliminating the need of full settling of the voltage on the sampling capacitor charged by a voltage reference.
To overcome the drawback, the present invention proposes a novel topology of signal independent voltage reference loading for the pipelined ADC.